Delay circuit which is free from temperature variation, power supply voltage variation and process variation

ABSTRACT

A delay circuit for delaying a digital input signal has a ramp generator, a logic circuit which provides a delayed output when the ramp voltage reaches threshold voltage, and a bias circuit which provides bias voltage to the ramp generator so that the delayed output is free from temperature variation, power supply voltage variation and process variation of semiconductor elements.

BACKGROUND OF THE INVENTION

The present invention relates to a delay circuit for a digital signal suitable for an integrated circuit, in particular, relates to such a delay circuit which is free from temperature variation, power supply voltage variation and/or variation of the production process. The delay time in the present delay circuit is obtained by charging and/or discharging a capacitor through a current source which uses a MOS field effect transistor (FET) to generate a ramp voltage, and determining the delay time by the time until said ramp voltage reaches a threshold level of a logic circuit.

A delay circuit for delaying a digital signal by a predetermined time is essential in a digital circuit field including a personal computer, and/or a digital measurement apparatus, for adjusting the timing of control signals.

Conventionally, a delay circuit has been implemented by using a hybrid IC circuit having an LC delay element and a logic gate for input/output buffer. However, a delay circuit in the form of a monolithic IC has been desired for producing a miniaturized and/or low cost device.

A delay circuit which is suitable for a monolithic integrated circuit has been known by charging or discharging a capacitor through a current source with a MOS field effect transistor to generate a ramp voltage, and the delay time is defined by the time until the ramp voltage reaches a threshold level of a logic circuit.

FIG. 12 shows a circuit diagram of a prior delay circuit which uses a ramp voltage. In the figure, the symbol M₁ is a first MOS field effect transistor, M₂ is a second MOS field effect transistor, C is a capacitor, Q₁ is a logic circuit, V_(BIAS) is DC bias potential, V_(DD) is DC power supply voltage, V_(IN) is an input terminal of a digital signal which is subject to delay, and V_(OUT) is an output terminal of a delayed signal.

In the above embodiment, the first MOS field effect transistor M₁ which is a P channel element, has a gate G₁ which is coupled with an input terminal V_(IN), and, a source S₁ which is coupled with power supply voltage V_(DD). The second MOS field effect transistor M₂ which is N channel element has a drain D₂ which is connected to the drain D₁ of the first transistor M₁, and the source S₂ which is grounded. The gate G₂ of the second transistor M₂ receives the DC (direct current) bias voltage V_(BIAS). The capacitor C is coupled between the point (a) which is junction point of the drains D₁ and D₂ of two transistors, and the ground. The logic circuit Q₁ is coupled with the point (a), and provides a logic output signal depending upon the charge in the capacitor C to provide the delayed output signal V_(OUT). The logic circuit Q₁ in the embodiment is implemented by an inverter, which provides low level output when the potential of the point (a) is higher than the threshold level of the inverter, and provides high level output when the potential of the point (a) is lower than said threshold level.

FIG. 13 shows the operational waveforms of the circuit. When an input digital signal V_(IN) is in low level, both the transistors M₁ and M₂ are active, and the potential on the point (a) is determined by the divisional ratio of the power potential V_(DD) by two transistors M₁ and M₂. When the ratio (W/L) of the gate width W to the channel length L of the first transistor M₁ is considerably large as compared with that of the second transistor M₂, the potential at the point (a) is at high level as shown in FIG. 13(b), and the potential is approximately V_(DD). The voltage between the gate and the source of, the first transistor M₁ is larger than that of the second transistor M₂.

When the digital input signal V_(IN) changes to high level at time t₀ as shown in FIG. 13(a), the first transistor M₁ becomes to cutoff state, and therefore, the charge on the capacitor C begins to discharge through the second transistor M₂. The gate G₂ of the second transistor M₂ receives the DC bias voltage V_(BIAS), and it functions as a constant current source in the saturation region where the following equation is satisifed.

    V.sub.DS ≦V.sub.GSN -V.sub.TN

where V_(DS) is the voltage between the drain and the source, V_(GSN) is equal to V_(BIAS), and V_(TN) is the threshold voltage.

Accordingly, when the digital input signal V_(IN) changes to high level, the potential at the point (a) decreases with approximate linearly as shown in FIG. 13(b).

The potential on the point (a) is monitored by a logic circuit Q₁ which is implemented by an inverter, which changes the output signal V_(OUT) from low level to high level as shown in FIG. 13(c), when the input voltage reaches the threshold voltage V_(TH) at time t₁.

The delay time T_(d) is the duration between the rising edge of the digital input signal V_(IN) and the rising edge of the output signal of the inverter Q₁.

The delay time T_(d) is shown by the following equation.

    T.sub.d =(V.sub.DD -V.sub.TH)·C/I.sub.DN

where T_(TH) which is the threshold voltage of the logic circuit Q₁, and is expressed as follows provided that the logic circuit Q₁ is implemented by a CMOS inverter.

    V.sub.TH =(βV.sub.DD +βV.sub.TP +V.sub.TN)/(1+β)

    β=[(L.sub.n ·W.sub.p ·μ.sub.p)/L.sub.p ·W.sub.n ·μ.sub.n)].sup.1/2

where V_(TN) (positive), L_(n), and W_(n) are the threshold voltage, channel length, and the gate width, respectively, of the N-channel element which constitutes a CMOS inverter, μ_(n) is a mobility of an electron which is a carrier in an N-channel element, V_(TP) (negative), L_(p), and W_(p) are the threshold voltage, the channel length, and the gate width, respectively, of the P-channel element which constitutes a CMOS inverter, and μ_(p) is the mobility of a positive hole which is the carrier in a P-channel element.

It should be noted in the above equations that the threshold voltage V_(TH) depends upon the source voltage V_(DD). For instance, when β=1, V_(TN) =|V_(TP) |, then T_(TH) =0.5V_(DD).

Further, I_(DN) in said equation for providing the delay time T_(d) is the drain current of the second transistor M₂, and is approximately obtained by the following equation.

    I.sub.DN =(W.sub.N /L.sub.N)(μ.sub.N C.sub.0 /2)(V.sub.GSN -V.sub.TN).sup.2

where V_(TN), L_(N) and W_(N) are the threshold voltage, the channel length and the gate width, respectively, of the second transistor M₂, μ_(N) is the mobility of an electron which is the carrier of the second transistor M₂, C₀ is the gate capacity for unit area of the second transistor M₂.

However, a prior delay circuit as described in FIGS. 12 and 13 has the following disadvantages.

a) As apparent in said equation of I_(DN), when the carrier mobility μ_(N) changes, the drain current I_(DN) changes, and then, the delay time T_(d) changes. The carrier mobility μ_(N) becomes small when the temperature becomes high. Therefore, the delay time T_(d) becomes longer depending upon the temperature rise.

b) As apparent from the equation for the threshold voltage V_(TH), the threshold voltage V_(TH) changes depending upon the channel length L_(p) or L_(n), the gate width W_(p) or W_(n), the mobility μ_(n) or μ_(p), and the threshold voltage V_(Tn) or V_(Tp), because of the change of the manufacturing process condition.

Further, as apparent from the equation of I_(DN), the drain current I_(DN) of the second transistor M₂ changes, depending upon the channel length L_(N), the gate width W_(N), the gate capacity C₀, and the threshold voltage V_(TN) because of the manufacturing process change. Thus, the delay time depends upon the error in the production process of transistors.

c) As apparent from the equation of T_(d), the delay time T_(d) is proportional to (V_(DD) -V_(TH)) which is the difference between the power voltage V_(DD) and the threshold voltage V_(TH) of an inverter, the delay time depends upon the power supply voltage V_(DD).

SUMMARY OF THE INVENTION

It is an object of the present invention to overcome the disadvantages and limitations of a prior delay circuit by providing a new and improved delay circuit.

It is also an object of the present invention to provide a delay circuit which is suitable for implementing an integrated circuit IC.

It is also an object of the present invention to provide a delay circuit in which a delay time is free from errors in the production process, temperature change, and power supply voltage change.

The above and other objects are attained by a delay circuit comprising of at least one ramp generator for providing a ramp voltage starting at digital input signal, a logic circuit accepting said ramp voltage and providing digital output signal which is delayed by a predetermined duration from said digital input signal when said ramp voltage reaches a predetermined threshold voltage, and a bias means for providing bias voltage to said ramp generator; said ramp generator comprising, a switching means comprising a first MOSFET which is switched ON and OFF by said digital input signal, a charge/discharge means comprising a second MOSFET, a resistor which is connected in series to a drain-source circuit of said second MOSFET, and an operational amplifier with an output coupled with a gate of said second MOSFET, a negative input coupled with junction of said resistor and said second MOSFET, and a positive input which accepts a bias voltage, and a capacitor which is charged and/or discharged through said charge/discharge circuit, and provides said ramp voltage across the capacitor; said bias means comprising at least one of means for providing voltage proportional to temperature variation and means for providing voltage proportional to said threshold voltage of said logic circuit.

In one modification, a current mirror circuit is coupled with said charge/discharge means so that a single bias means is enough for a plurality of delay circuits which are subject to compensate temperation change, power supply change, and/or production error.

Still preferably, a pair of delay circuits which receives a common digital input signal in opposite polarity are used to provide a delayed output signal in which both beginning edge and rear edge of an input pulse are delayed.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features, and attendant advantages of the present invention will be appreciated as the same become better understood by means of the following description and accompanying drawings wherein;

FIG. 1 is a circuit diagram of the delay circuit of the first embodiment according to the present invention,

FIG. 2 shows operational waveforms in the circuit of FIG. 1,

FIG. 3 shows a circuit diagram of a bias means 1 in FIG. 1,

FIG. 4 is a circuit diagram of another embodiment according to the present invention,

FIG. 5 is a circuit diagram of a bias means 1 in FIG. 4,

FIG. 6 is a circuit diagram of still another embodiment of the delay circuit according to the present invention,

FIG. 7 is a circuit diagram of still another embodiment of the delay circuit according to the present invention,

FIG. 8 is a circuit diagram of still another embodiment of the delay circuit according to the present invention,

FIG. 9 shows operational waveforms of the circuit of FIG. 8,

FIG. 10 is a circuit diagram of still another embodiment of the delay circuit according to the present invention,

FIG. 11 shows the operational waveforms of the circuit of FIG. 11,

FIG. 12 shows a prior delay circuit, and

FIG. 13 shows operational waveforms of the circuit of FIG. 12.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a circuit diagram of the delay circuit according to the present invention. The same reference numerals as those in FIG. 12 show the same members.

The basic idea of the present invention to provide a delay time which is free from temperature change, power supply voltage variation, and process variation is (1) the use of a resistor R_(c) inserted one end of a transistor and power supply (or ground), and to keep constant current in the resistor R_(c) and (2) to compensate for the change of the threshold level of the inverter Q₁, by adjusting the bias voltage which is applied to the gate of the second transistor M₂.

In FIG. 1, the symbol R shows a ramp generator for providing a ramp voltage starting with a digital input signal V_(IN), and Q₁ shows an inverter which provides a digital output signal V_(OUT) when said ramp voltage reaches the predetermined threshold voltage of the inverter. The ramp generator R has a switching means implemented by a first MOSFET M₁ which is switched ON and OFF by a digital input signal V_(IN), a charge/discharge circuit having a resistor R_(c), a second MOSFET M₂ and an operational amplifier A_(O), and a capacitor C coupled with power supply voltage V_(DD) through said charge/discharge circuit. The operational amplifier A_(O) receives the bias voltage V_(x) which compensates temperature variation, power supply variation, and process variation.

The first MOSFET (metal oxide semiconductor field effect transistor) M₁ is composed of an N-channel element, with a gate G₁ coupled with a digital input signal V_(IN) which is subject to delay, and a source S₁ which is grounded as one port of the power supply.

The second MOSFET M₂ is composed of a P-channel element with a drain D₂ coupled with a drain D₁ of the first transistor M₁, and a source S₂ coupled with the power supply voltage V_(DD) through the resistor R_(c). The power supply voltage V_(DD) is DC voltage for operating the delay circuit.

The operational amplifier A₀ has a positive input (+), a negative input (-), and an output which is coupled with the gate G₂ of the second transistor M₂. The negative input (-) is coupled with the junction of the source S₂ of the second transistor M₂ and the resistor R_(c).

The numeral 1 shows a bias means for providing a voltage V_(x) to the operational amplifier A₀. The bias means 1 comprises a first compensation voltage generator 101 which provides the voltage V_(a) which is not affected by temperature change, a second compensation voltage generator 102 which provides the voltage V_(b) which changes linearly according to temperature change, a third compensation voltage generator 103 which provides the threshold voltage V_(TH) of the logic circuit Q₁, and the voltage combiner 104 which combines the voltages V_(a), V_(b), V_(TH), and the power supply voltage V_(DD). The voltage combiner 104 has an operational amplifier A₁₁, and a voltage adder A₁₂.

The operational amplifier A₁₁ functions as an adder, having a negative input terminal (-) connected to the voltage adder A₁₂ through the resistor R₁₁ and the positive input terminal (+) which is coupled with the power supply voltage V_(DD) through the resistor R₁₂ and grounded through the resistor R₁₃. The resistor R_(f1) is connected between the negative input terminal (-) and the output of the amplifier A₁₁. The output of the amplifier A₁₁ provides the bias voltage V_(x) which is applied to the positive input of the operational amplifier A₀. The resistance of the resistors R_(f1) and R₁₂ is selected to be (K₁ ·R_(a1)) where R_(a1) is resistance of the resistors R₁₁ and R₁₃, and K₁ is constant.

The voltage adder A₁₂ provides the combined DC sum V₀₁ as follows.

    V.sub.01 =V.sub.TH +V.sub.b -V.sub.a

The sum V₀₁ of the output of the voltage adder A₁₂ is applied to the negative input (-) of the operational amplifier A₁₁ through the resistor R₁₁. The positive input (+) of the operational amplifier A₁₁ receives the input voltage which divides the power supply voltage V_(DD) by the resistors R₁₂ and R₁₃. Thus, the output V_(x) of the operational amplifier A₁₁ is;

    V.sub.x =V.sub.DD -K.sub.1 V.sub.01

The voltage V_(x) which is the output of the operational amplifier A₁₁ is applied to the positive input (+) of the operational amplifier A₀, which functions so that the voltages at two input terminals (-) and (+) are equal to each other. Therefore, the junction (b) of the source S₂ of the second FET M₂ and the resistor R₂ is at the potential equal to V_(x).

FIG. 2 shows the operational waveforms of the apparatus of FIG. 1. When a digital input signal V_(in) (FIG. 2(a)) is at high level, both the FET's M₁ and M₂ are in active state. Provided that the ratio (W/L) of the gate width W to the channel length L of the first FET M₁ is sufficiently larger than than (W/L) of the second FET M₂, then, the voltage between the gate and the source of the first FET M₁ is higher than that of the second FET M₂, the potential at the point (a) which is the junction of the drains D₁ and D₂ of two FET's is at low level (0 volt) as shown in FIG. 2(b).

When the digital input signal V_(IN) turns to low level at the time t₀ as shown in FIG. 2(a), the first FET M₁ goes to a cutoff state, and the capacitor C is charged through the resistor R_(c) and the second FET M₂. Therefore, the potential at the point (a) at one end of the capacitor C increases as shown in FIG. 2(b). The potential at the point (a) is applied to the inverter Q₁, which turns an output signal from high level to low level at the time t₁ when the potential at the point (a) reaches the threshold level V_(TH) of the inverter Q₁ as shown in FIG. 2(c).

The delay time T_(d) is the time between t₀ and t₁ until the inverter Q₁ provides an output signal V_(OUT), and is expressed as follows.

T_(d) =(V_(TH) ·C)/I_(DP)

where I_(DP) is drain current of the second FET M₂, and is equal to the charge current of the capacitor C.

Since the operational amplifier A₀ functions to adjust the potential at the point (b) which is the junction of the source S₂ of the second FET M₂ and the resistor R_(c) equal to the potential V_(x), the current I_(DP) is expressed as follows.

    I.sub.DP =(V.sub.DD -V.sub.x)/R.sub.c

It should be noted in the above equation that the use of the operational amplifier A₀ which provides the potential V_(x) at one end of the resistor R_(c) removes the delay time error because of the process error of a semiconductor, since the current I_(DP) is determined only by V_(DD) and R_(c), but is free from mobility, and/or gate capacitance of semiconductor elements.

The delay time T_(d) is expressed as follows. ##EQU1##

In order to prevent the change of T_(d) by the change of the source voltage and temeperature, (V_(DD) -V_(x)) must be proportional to V_(TH), and the temperature coefficient of (V_(DD) -V_(x)) must be equal to the temperature coefficient α of the resistor R_(c).

In other words, the bias voltage V_(x) must satisfy the following equation (2).

    (V.sub.DD -V.sub.x)=K.sub.1 [V.sub.TH +K.sub.0 (T-T.sub.0) (2)

In the equation (2), (V_(DD) -V_(x)) which is the denominator of the equation (1) has the positive temperature coefficient K₀ (V/°C.), and has the value K₁ ·V_(TH) which is proportional to the threshold voltage V_(TH) at the reference temperature T₀. The value K₁ is constant.

The delay time T_(d) is then obtained by the equation (3) by combining the equations (2) and (1).

    T.sub.d =C·R.sub.0 [1+α(T-T.sub.0)]V.sub.TH /[K.sub.1 (V.sub.TH +K.sub.0 (T-T.sub.0))]=C·R.sub.0 [1+α(T-T.sub.0)]V.sub.TH /[K.sub.1 V.sub.TH (1+β(T-T.sub.0)))](3)

where β=K₀ /V_(TH).

Provided that K₀ =α·V_(TH), and α=β are satisfied, the delay time T_(d) is;

    T.sub.d =C·R.sub.0 /K.sub.1                       (4)

The equation (4) shows that the delay time T_(d) is free from temperature variation, power voltage variation, and process variation.

FIG. 3 shows a circuit diagram of the bias means 1 which provides the bias voltage V_(x) for satisfying above equations (2) through (4). The first compensation voltage generator 101 which provides the voltage V_(a) which is free from temperature change has an operational amplifier A₂₁, a pair of bipolar transistors Q₁₁ and Q₂₁ having the different emitter area from each other in diode connection, the resistors R₃₁, R₃₂ and R₃₃, and the other operational amplifier A₂₂. The operational amplifier A₂₁ has the positive input connected to the emitter of the bipolar transistor Q₁₁, and the negative input (-) connected to the junction of the resistors R₃₁ and R₃₂.

The operational amplifier A₂₂ has the negative input (-) connected to the output of the operational amplifier A₂₁ through the resistor R₄₁, and the positive input (+) connected to the power source V_(DD) through the resistor R₄₂ and the ground through the resistor R₄₃. The output of the amplifier A₂₂ is connected to the negative input (-) through the feedback resistor R_(f3). The resistance of the resistors R₄₃ and R_(f3) is selected to be K₂ ·R_(a2) where R_(a2) is the resistance of the resistors R₄₁ and R₄₂.

The second compensation voltage generator 102 for generating the voltage V_(b) which changes linearly according to temperature change has the operational amplifier A₃₁, a pair of bipolar transistors Q₃₁ and Q₄₁ having the different emitter area from each other in diode connection, the resistors R₅₁, R₅₂ and R₅₃, and the operational amplifier A₃₂. The operational amplifier A₃₁ has the positive input (+) connected to the emitter of the bipolar transistor Q₃₁, and the negative input (-) connected to the junction of the resistors R₅₁ and R₅₂. The operational amplifier A₃₂ has the negative input (-) connected to the output of the amplifier A₃₁ through the resistor R₆₁, and the positive input (+) connected to the power source voltage V_(DD) through the resistor R₆₂ and the ground through the resistor R₆₃. The output of the amplifier A₃₂ is connected to the negative input through the feedback resistor R_(f4). The resistance of the resistors R₆₁ through R₆₃, and the feedback resistor F_(f4) is essentially the same as one another (=R_(a3)).

The third compensation voltage generator 103 for providing the threshold voltage V_(TH) of the inverter Q₁ has a logic circuit Q₅₁ and an operational amplifier A₄₁. The logic circuit Q₅₁ is the same inverter as the inverter Q₁, mounted on the same semiconductor substrate as that of Q₁. The output of the inverter Q₅₁ is connected to the input of the same. It should be noted that the output of the all feedback type inverter in which the output is connected to the input, is equal to the threshold voltage of the own inverter. Therefore, the logic circuit Q₅₁ provides the threshold voltage V_(TH) of the inverter Q₁. The output of the inverter Q₅₁ is applied to the positive input of the operational amplifier A₄₁ which composes an impedance converter with the unit gain in the unity feedback connection so that the threshold voltage V_(TH) is output with low impedance.

The combiner 104 has the operational amplifiers A₁₁ and A₁₂. The operational amplifier A₁₂ has the negative input (-) connected to the output V_(a) of the means 101 which provides the voltage V_(a) free from temperature, and the positive input (+) connected to the output V_(b) which changes linearly according to temperature change through the resistor R₂₂ and the threshold voltage V_(TH) through the resistor R₂₃. The resistor R_(f2) is a feedback resistor. The resistance of the resistors R₂₁ through R₂₃ and F_(f2) is essentially the same as one another (=R_(a4)).

In the above structure, the output voltage V₁ of the operational amplifier A₂₁ in the compensation voltage generator 101, and the output voltage V₂ of the operational amplifier A₃₁ of the second compensation voltage generator 102, are expressed as follows, respectively.

    V.sub.1 =V.sub.DD -[V.sub.BE1 +V.sub.p1 (T)]               (5)

    V.sub.2 =V.sub.DD -[V.sub.BE3 +V.sub.p2 (T)]               (6)

where;

V_(p1) (T)=(kT/q)(R₃₂ /R₃₁)ln[(I₁ /I₂)(S₂ /S₁)]=(kT/q)(R₃₂ /R₃₁)ln[(R₃₂ /R₃₁)(S₂ /S₁)]

V_(p2) (T)=(kT/q)(R₅₂ /R₅₁)ln[I₃ /I₄)(S₄ /S₃)]=(kT/q)(R₅₂ /R₅₁)ln[R₅₂ /R₅₃)(S₄ /S₃)]

k; Boltzmann's constant

T; absolute temperature

q; charge of an electron

S₁ ; area of an emitter of a bipolar transistor Q₁₁

S₂ ; area of an emitter of a bipolar transistor Q₂₁

S₃ ; area of an emitter of a bipolar transistor Q₃₁

S₄ ; area of an emitter of a bipolar transistor Q₄₁

V_(BE1) ; voltage between a base and an emitter of a bipolar transistor Q₁₁

V_(BE3) ; voltage between a base and an emitter of a bipolar transistor Q₃₁

It should be appreciated that voltages V_(BE1) and V_(BE3) have the negative temperature coefficient about -2 mV/°C., and V_(p1) (T) and V_(p2) (T) are proportional to absolute temperature (T).

According to the present invention, the voltage V₁ is determined so that the temperature coefficient in the equation (5) is zero, and V₂ is determined so that the temperature coefficient in the equation (6) is constant (K₀ =αV_(TH) mV/°C.).

The conditions that the temperature coefficient of V₁ is zero are as follows n the equation (5).

    (αV.sub.BE1 /αT)+(αV.sub.p1 (T)/αT)=0, and

    (αV.sub.BE1 /αT)+(k/q)(R.sub.32 /R.sub.31)ln[(R.sub.32 R.sub.33)(S.sub.2 /S.sub.1)]=0

Assuming that;

    (αV.sub.BE1 /αT)=-2 [mV/°C.], R.sub.32 =R.sub.33, and S.sub.2 /S.sub.1 =10

then, the temperature coefficient of V_(BE1) +V_(p1) (T) is zero by designing the ratio R₃₂ /R₃₃ as follows.

    R.sub.32 /R.sub.31 =-(αV.sub.BE1 /αT)/[(k/q)ln[(R.sub.32 /R.sub.33)(S.sub.2 /S.sub.1)]]=2.0/[(0.085)ln(10)]=10

Assuming that the reference temperature T₀ is 300° K. (absolute temperature), and V_(BE1) at that reference temperature is 0.7 V, then, the following equation is satisfied.

    V.sub.BE1 (T.sub.0)+V.sub.p1 (T.sub.0)=0.7+(0.085.10.sup.-3)(300)(10)ln(10)=1.3 [V]

That voltage is free from the temperature change and the power supply voltage change, and is defined as a constant voltage V_(REF1), and then,

    V.sub.1 =V.sub.DD -V.sub.REF1

On the other hand, the conditions that V₂ has the temperature coefficient K₀ (mV/°C.) in the equation (6) are as follows.

    (αV.sub.BE3 /αT)+(αV.sub.p2 (T)/αT)=K.sub.0, and

    (αV.sub.BE3 /αT)+(k/q(R.sub.52 /R.sub.51)ln[(R.sub.52 /R.sub.53)(S.sub.4 /S.sub.3)]=k.sub.0

where K₀ =αV_(TH).

Assuming in a numerical embodiment that α=800 [ppm/°C., and V_(TH) =2.5 V, then,

    K.sub.0 =αV.sub.TH =2.0 [mV/°C.]

Assuming that (αB_(BE3) /αT)=-2 (mV/°C.), and R₅₂ =R₅₃, and S₄ /S₃ =20, the ratio of R₅₂ /R₅₁ for satisfying above conditions is;

    R.sub.52 /R.sub.51 =[K.sub.0 -αV.sub.BE3 /αT)/((k/q)ln((R.sub.52 /R.sub.53)(S.sub.4 /S.sub.3))]=(2.0-(-2.0))/(0.085)ln(20)=16

Therefore, when R₅₂ =R₅₃, S₄ /S₃ =20, and R₅₂ /R₅₁ =16, the temperature coefficient of V_(BE3) +V_(p2) (T) is;

    αV.sub.TH =+2.0 [mV/°C.]

Since the voltage V₂ includes the power supply voltage V_(DD), that power supply voltage V_(DD) is subtracted from V₂ by using the operational amplifier A₃₂, which provides the output V_(b) ;

    V.sub.b =V.sub.DD -V.sub.2 =V.sub.BE3 +V.sub.p2 (T)

That voltage V_(b) =V_(BE3) +V_(p2) (T) has the temperature coefficient αV_(TH) =+2.0 mV/°C.

Next, the offset voltage V_(b) (T₀) is subtracted from V_(b) in order to provide the compensation voltage with the temperature coefficient K₀, and the value zero (0) at the reference temperature (T₀), as shown in the equation (2). That offset voltage is derived from the reference voltage V_(REF1) obtained in the first compensation voltage generator 101.

As the voltage V₁ in the first compensation voltage generator 101 includes the power supply voltage V_(DD), the operational amplifier A₂₂ effects the subtraction V_(DD) -V₁, and provides the factor K₂.

    V.sub.a =K.sub.2 (V.sub.DD -V.sub.1)=K.sub.2 ·V.sub.REF1

The factor K₂ must satisfy the following condition so that V_(b) (T₀)=V_(BE3) (T₀)+V_(p2) (T₀) is satisfied (the value V_(b) is zero at reference temperature T₀).

    K.sub.2 ·V.sub.REF1 =V.sub.BE3 (T.sub.0)+V.sub.p2 (T.sub.0)=V.sub.BE3 (T.sub.0)+(k/q)(R.sub.52 /R.sub.51)(T.sub.0)ln[(R.sub.52 /R.sub.53)(S.sub.4 /S.sub.3)]

Assuming that V_(BE3) (T₀)=0.7 V, R₅₂ =R₅₃, S₄ /S₃ =20, R₅₂ /R₅₁ =16, and V_(REF1) =1.3 V, then, the value K₂ is obtained as follows.

    K.sub.2 ·V.sub.REF1 =V.sub.BE3 (T.sub.0)+(k/q)(R.sub.52 /R.sub.51)(T.sub.0)ln[(R.sub.52 /R.sub.53)(S.sub.4 /S.sub.3)]=1.9

    K.sub.2 =1.9/V.sub.REF1 =1.9/1.3=1.5

The operational amplifier A₁₂ functions as an adder, providing the output voltage V₀₁ : ##EQU2## Thus, the operational amplifier A₁₂ effects the subtraction V_(b) -V_(a), and the threshold voltage V_(TH) which is the output of the operational amplifier A₄₁ is added to the difference V_(b) -V_(a).

The operational amplifier A₁₁ effects the subtraction and the output V_(x) is; ##EQU3## The value V_(x) is obtained by applying V_(DD) to the positive input and V₀₁ to the negative input of the operational amplifier A₁₁. The factor K₁ is determined by the resistance of the resistors R₁₁ through R₁₃ and the feedback resistor R_(f1).

It is preferable that the factor K₁ is less than 1 (K₁ <1) so that the ramp voltage has some desired level, considering the dynamic range of the operational amplifier A₀, and the ratio (W/L) in size of the second FET M₂, and that the voltage drop in the resistor R_(c) is preferably low.

The npn bipolar transistors Q₁₁, Q₂₁, Q₃₁ and Q₄₁ are produced through P well C-MOS process with an emitter by an n⁺ diffusion layer which is produced through the same steps as those of a source/drain of an N channel MOS FET, a base with a P well, and a collector with an N type substrate.

It should be noted in FIGS. 1 through 3 that the use of only compensation means 101 and 102 is useful for compensating only temperature change. Similarly, the use of only the compensation means 103 is useful for compensating the change of the threshold voltage. Of course, when those three means 101, 102 and 103 are used, both the temperature change and threshold voltage change are compensated for.

FIG. 4 shows a circuit diagram of another embodiment of the present invention. In FIG. 4, the same numerals as those in FIG. 1 show the same members. The feature of FIG. 4 as compared with FIG. 1 is that the resistor R_(c) is coupled in the ground side, instead of the power source side.

The ramp voltage in FIG. 4 is decreasing in voltage as shown in FIG. 13, while the ramp voltage in FIG. 1 is increasing in voltage as shown in FIG. 2(b).

The first MOSFET M₁ is composed of a P-channel element with a gate G₁ accepting an input digital signal V_(IN) which is subject to be delayed, and a source S₁ connected to the power supply voltage V_(DD).

The second MOSFET M₂ is composed of an N-channel element, with a drain D₂ connected to the drain D₁ of the first FET M₁, the source S₂ grounded through the resistor R_(c).

In this embodiment, the capacitor C is charged when the digital input signal V_(IN) is in low level and the first FET M₁ is conducted, and said capacitor C is discharged through the second FET M₂ and the resistor R_(c) provides a ramp voltage when the digital input signal V_(IN) is in high level and the first FET M₁ is in cutoff state. The voltage across the capacitor C, or the potential at the point (a) is converted to a digital form by a logic circuit Q₁ which has the threshold voltage V_(TH), and provides the delayed signal. The operational waveforms in FIG. 4 are the same as those in FIG. 13.

The bias means 1 has a first voltage generator 101 which provides a compensation voltage V_(a) free from temperature variation, a second voltage generator 102 which provides a compensation voltage V_(b) which is linear to temperature variation, a third voltage generator 104 which provides the threshold voltage V_(TH) of the inverter Q₁, and a voltage combiner 104.

The operational amplifier A₀ has the positive input (+) and the negative input (-) and the output. The negative input (-) is connected to the source S₂ of the second FET M₂, the output is connected to the gate G₂ of the second FET M₂.

The voltage combiner 104 provides the DC voltage V_(x) by using the outputs of the means 101, 102, 103, and the power source voltage V_(DD).

The voltage combiner 104 has an operational amplifier A₁₁ and a voltage adder A₁₂. The operational amplifier A₁₁ composes an adder with a negative input (-) connected to the threshold voltage V_(TH) through the resistor R₁₁, and a positive input (+) connected to the power supply voltage V_(DD) through the resistor R₁₂, and grounded through the resistor R₁₃. The output of the amplifier A₁₁ is connected to the negative input (-) through the resistor R_(f1), and applied to said voltage adder A₁₂. The resistance of the resistors R_(f1) and R₁₃ is designed to be K₁ ·R_(a1), where R_(a1) is the resistance of the resistors R₁₁ and R₁₂, and K₁ is constant. The output of the operational amplifier is K₁ (V_(DD) -V_(TH)).

The voltage adder A₁₂ provides the DC voltage V_(x) as follows.

    V.sub.x =K.sub.1 (V.sub.DD -V.sub.TH)+(V.sub.DD -V.sub.a)-(V.sub.DD -V.sub.b)=K.sub.1 (V.sub.DD -V.sub.TH)+V.sub.b -V.sub.a

The DC voltage V_(x) is applied to the positive input (+) of the operational amplifier A₀, which provies the bias voltage to the second FET M₂ so that the potential at the resistor R_(c) is equal to the DC voltage V_(x).

The delay time T_(d) in FIG. 4 is shown below.

    T.sub.d =(V.sub.DD -V.sub.TH)·C/I.sub.DN

where I_(DN) is drain current of the second FET M₂, and is the discharge current from the capacitor C.

As the voltage across the resistor R_(c) is V_(x), the discharge current I_(DN) is;

    I.sub.DN =V.sub.x /R.sub.c

Therefore, the delay time T_(d) is; ##EQU4## where α is temperature coefficient of the resistor R_(c), and is expressed as follows.

    α=(1/R.sub.c)(αR.sub.c /αT)

R₀ is the resistance of the resistor R_(c) at the reference temperature T₀.

It should be noted in the above equations that the conditions to have delay time free from temperature variation are that the voltage V_(x) is proportional to the voltage (V_(DD) -V_(TH)), and that the temperature coefficient of the voltage V_(x) is equal to the temperature coefficient α of the resistor R_(c). In other words, the voltage V_(x) must be expressed as follows, where K₀ is positive temperature gradient (V/°C.), and K₁ is constant.

    V.sub.x =K.sub.1 +(V.sub.DD -V.sub.TH)+K.sub.0 (T-T.sub.0) (8)

When the relation of the equation (8) is inserted into the equation (7), the following equation is obtained.

    T.sub.d =C·R.sub.0 ·[1+α(T-T.sub.0)]·(V.sub.DD -V.sub.TH)/[K.sub.1 (V.sub.DD -V.sub.TH)+(T-T.sub.0)]=C·R.sub.0 [1+α(T-T.sub.0)]·(V.sub.DD -V.sub.TH)/[K.sub.1 (V.sub.DD -V.sub.TH)·[1+β(T-T.sub.0)]                 (9)

where β=K₀ /[K₁ (V_(DD) -V_(TH))]When K₀ =α·K₁ (V_(DD) -V_(TH)), and α=β are satisfied, the delay time T_(d) is expressed as follows, and that delay time T_(d) is free from temperature variation, power supply voltage, and producing process.

    T.sub.d =C·R.sub.0 /K.sub.1                       (10)

FIG. 5 shows a circuit diagram of the bias means 1, which satisfies the above conditions in the equations 8 through 10.

The voltage generator 101 which provides the voltage V₁ free from the power supply voltage variation has an operational amplifier A₂₁, a pair of pnp bipolar transistors Q₁₁ and Q₂₁ having different emitter area from each other in diode connection, resistors R₃₁, R₃₂ and R₃₃, and another operational amplifier A₂₂. The operational amplifier A₂₁ has a positive input (+) connected to an emitter of a bipolar transistor Q₁₁, and a negative input (-) connected to a junction of the resistors R₃₁ and R₃₂. The operational amplifier A₂₂ has a negative input (-) connected to output of the operational amplifier A₂₁ through the resistor R₄₁, and the positive input (+) connected to the power supply voltage V_(DD) through the resistor R₄₃ and is grounded through the resistor R₄₂. The output of the amplifier A₂₂ is connected to the negative input (-) through the resistor R_(f3). The resistance of the resistors R₄₃ and R_(f3) is (K₂ ·R_(a2)) where R_(a2) is resistance of the resistors R₄₁ and R₄₂.

The voltage generator 102 for providing the voltage V₂ which is linear to temperature change has an operational amplifier A₃₁, a pair of npn bipolar transistors Q₃₁, and Q₄₁, the resistors R₅₁, R₅₂ and R₅₃, and the other operational amplifier A₃₂. The operational amplifier A₃₁ has a positive input (+) connected to an emitter of the bipolar transistor R₅₃, and a negative input (-) connected to a junction of the resistors R₅₁ and R₅₂. The operational amplifier A₃₂ has a negative input (-) connected to an output of the operational amplifier A₃₁ through the resistor R₆₁, and a positive input (+) connected to the power supply voltage V_(DD) through the resistor R₆₃ and is grounded through the resistor R₆₂. The output of the operational amplifier A₃₂ is connected to the negative input (-) through the feedback resistor R_(f4). The resistance of the resistors R₆₁ through R₆₃, and the resistors R_(f4) is the same as one another, and is expressed as R_(a3).

The voltage generator 103 for taking the threshold voltage V_(TH) of the logic circuit Q₁ has the logic circuit Q₅₁, and the operational amplifier A₄₁. The logic circuit Q₅₁ is similar to the logic circuit Q₁ in FIG. 4, and the output of Q₅₁ is connected to the input of the same. The output voltage of a full feedback type inverter which connects the output to the input is equal to the threshold voltage of the inverter itself. So, the logic circuit Q₅₁ provides the voltage which is essentially equal to the threshold voltage V_(TH) of the logic circuit Q₁.

The output V_(TH) is applied to the positive input (+) of the operational amplifier A₄₁, which constitutes an impedance converter with unit gain by unity feedback connection, and provides the low impedance output voltage V_(TH).

The voltage combiner 104 has operational amplifiers A₁₁ and A₁₂. The operational amplifier A₁₁ has a negative input (-) connected to the output of the operational amplifier A₄₁, and a positive input (+) connected to the power voltage V_(DD) through the resistor R₁₂ and is grounded through the resistor R₁₃ The resistor R_(f1) is a feedback resistor. The resistance of the resistors R₁₃ and R_(f1) is designed to be K₁ ·R_(a1), where R_(a1) is the resistance of the resistors R₁₁ and R₁₂. The operational amplifier A₁₂ has a negative input (-) connected to the output of the operational amplifier A₃₂ through the resistor R₂₁, and a positive input (+) connected to the output of the operational amplifier A₂₂ through the resistor R₂₂, and to the output of the operational amplifier A₁₁ through the resistor R₂₃. The resistor R_(f2) is a feedback resistor. The resistance of the resistors R₂₁ through R₂₃, and R_(f2) is the same as one another, and is R_(a4).

The operation of the embodiment of FIGS. 4 and 5 is similar to that of FIGS. 1 through 3.

The embodiment of FIGS. 1 through 3 is suitable to an N well C-MOS process, and the embodiment of FIGS. 4 and 5 is suitable to a P well C-MOS process.

FIG. 6 is still another embodiment of the delay circuit according to the present invention. The feature of FIG. 6 is the presence of a current mirror circuit B₁ enclosed by a dotted line.

The embodiment of FIG. 6 is the combination of the embodiment of FIG. 1 and the current mirror circuit B₁.

The embodiment of FIG. 6 is advantageous when there are a plurality of delay circuits each of which must compensate temperature variation, power voltage variation, and/or process variation. One example of that plurality of delay circuits is a transversal filter in which a plurality of delay circuits coupled in series to each other are used.

The embodiment of FIG. 6 has the advantage that the compensation circuit which is shown in left side of the line X--X is used common to all the delay circuits T₁, T₂, . . . , where T_(i) is a delay element, including a switching transistor M₁, a capacitor C and an inverter Q₁.

The digital input signals to each delay elements are designated as V_(IN) (1), V_(IN) (2) et al, and the output signals are designated as V_(OUT) (1), V_(OUT) (2) et al.

In the embodiment of FIG. 6, the first FET M₁ which receives a digital input signal V_(IN), and a second FET M₂ which receives a bias voltage V_(x) are composed of N-channel elements.

The current mirror circuit B₁ has a third MOSFET M₃ and a fourth MOSFET M₄. The third FET M₃ is a P-channel element, having a gate G₃ connected to a drain D₃, a source S₃ connected to the power supply voltage V_(DD), and said drain D₃ being connected to a drain D₂ of the second FET M₂. The fourth FET M₄ is a P-channel element having a gate G₄ connected to the gate G₃ of the third FET M₃ so that a current mirror circuit is composed, and a drain D₄ connected to the drain D₁ of the first FET M₁.

The operational waveforms in FIG. 6 are the same as those in FIG. 2. When an input digital signal V_(IN) (1) applied to the gate G₁ of the first FET M₁ is at high level, the first FET M₁ is conductive, and the potential at the point (a) is at low level, since the capacitor C discharges through the first FET M₁. When the digital input signal V_(IN) (1) changes to low level, the first FET M₁ is cutoff. The fourth FET M₄, which is biased by the third FET M₃, is in active state. As the fourth FET M₄ composes a current mirror circuit with the third FET M₃, the current flows in the fourth FET M₄ proportional to the current in the series circuit of the second FET M₂, the third FET M₃ and the resistor R_(c). The current in the fourth FET M₄ charges the capacitor C, and provides the ramp voltage.

The structure and the operation of the bias means 1 in FIG. 6 are the same as those in FIGS. 4 and 5. The embodiment of FIG. 6 provides the delay time free from temperature variation, power supply voltage variation and process variation.

FIG. 7 shows a circuit diagram of still another embodiment of the delay circuit according to the present invention, which is the combination of a current mirror circuit B₂ and the embodiment of FIG. 4.

In FIG. 7, the first FET M₁ and the second FET M₂ are composed of P-channel elements. The third FET M₃ and the fourth FET M₄ which compose the current mirror circuit B₂ are composed of N-channel elements.

The operational waveforms in FIG. 7 are the same as those in FIG. 13. When the digital input signal V_(IN) applied to the gate G₁ of the first FET M₁ is in low level, the first FET M₁ is conductive, and the capacitor C is charged. Thus, the potential at the point (a) at one end of the capacitor C is at a high level. When the digital input signal V_(IN) changes to a high level and the first FET M₁ is non-conductive, the capacitor C discharges through the fourth FET M₄ and the ramp voltage is obtained across the capacitor C. The discharge current in the fourth FET M₄ is proportional to the current in the path of the second FET M₂, the third FET M₃ and the resistor R_(c), because of the current mirror connection of the third FET M₃ and the fourth FET M₄.

The structure and the operation of the bias circuit 1 in FIG. 7 are the same as that in FIGS. 1 and 3.

It should be appreciated in FIGS. 6 and 7 that a single bias circuit 1 can compensate for the fluctuation of delay time of a plurality of delay circuits T_(i). In that case, the first FET M₁, the fourth FET M₄, the capacitor C and the inverter Q₁ compose a delay element, in which a gate G₁ of a first FET M₁ receives a digital input signal V_(IN), and a gate G₄ of a fourth FET M₄ receives a bias voltage from G₃ of a third FET M₃ which constitutes a current mirror circuit with a fourth FET M₄.

When a plurality of delay circuits are mounted on a semiconductor chip, only a delay element comprising a first FET M₁, a fourth FET M₄, a capacitor C and a logic circuit Q₁ must be mounted in plural, but, a single bias means in left portion from the line X--X in FIGS. 6 and 7 can be common to all the delay elements. Therefore, the area of a semiconductor chip can be reduced as compared with that in which no current mirror circuit is used. And, the power consumption is also reduced by the use of a current mirror circuit.

FIG. 8 shows a circuit diagram of still another embodiment of the delay circuit according to the present invention, and FIG. 9 shows the operational waveforms of the circuit of FIG. 8. In FIG. 8, a digital input signal V_(IN) is separated to two input signals by using a pair of inverters INV₁ and INV₂ so that the polarity of two signals is opposite of each other. The first delay circuit or ramp generator R₁ operates to delay the beginning edge of an input pulse, and the second delay circuit R₂ operates to delay the rear edge of an input pulse. The logic circuit Q₁ which includes a flip-flop FF combines the outputs of the first delay circuit R₁ and the second delay circuit R₂. The output V_(OUT) of the logic circuit Q₁ has the pulse width equal to that of a digital input pulse V_(IN), alternatively, the pulse width of the output pulse V_(OUT) may be designed arbitrarily.

The structure of each delay circuits R₁ and R₂ is essentially the same as that in FIG. 1.

The first delay circuit R₁ comprises a first MOSFET M₁₁, a second MOSFET M₂₁, a resistor R₁₀, an operational amplifier A₁₀, and a capacitor C₁. The gate G₂₁ of the first FET M₁₁ accepts the digital input signal V_(IN) in the polarity inverted form by the inverter INV₁.

The second delay circuit R₂ comprises a first MOSFET M₁₂, a second MOSFET M₂₂, a resistor R₂₀, an operational amplifier A₂₀, and a capacitor C₂. The gate G₁₂ of the first FET M₁₂ accepts the digital input signal V_(IN) through a pair of series connected inverters INV₁ and INV₂. The polarity of the input of the first FET M₁₂ is the same as that of the original signal V_(IN), because of two inverters.

The logic circuit Q₁ comprises a flip-flop FF and an inverter INV₃. The flip-flop FF has two NOR (not-OR) gates NOR₁ and NOR₂, which constitute a RS (set-reset) type flip-flop, which is set by the high level output signal of the first delay circuit R₁, and is reset by the high level output signal of the second delay circuit R₂.

The negative inputs (-) of each operational amplifiers A₁₀ and A₂₀ are connected to the sources S₂₁, and S₂₂, respectively, which are connected to the power source voltage V_(DD) through the resistors R₁₀ and R₂₀, respectively. The outputs of the operational amplifiers are applied to the gates G₂₁ and G₂₂ of the second FET's M₂₁, and M₂₂, respectively. The positive inputs (+) of the operational amplifiers A₁₀ and A₂₀ are commonly coupled with the output V_(x) of the bias means 1. The structure of the bias means 1 is substantially the same as that of FIG. 3, except that the inverter Q₅₁ in FIG. 3 is replaced to a NOR gate which has the same threshold voltage as that of NOR₁ and NOR₂.

When a digital input signal V_(IN) changes to high level at time t₀ as shown in FIG. 9(a), the potential at point (c) at the output of the inverter INV₁ changes to low level as shown in FIG. 9(b). The potential at the point (c) is applied to the gate G₁₁ of the first FET M₁₁ of the first delay circuit, and then, the ramp voltage begins to increase at time t₀ as shown in FIG. 9(c) as described in accordance with FIGS. 1 and 2. When that ramp voltage which is the potential at the point (d) at one end of the capacitor C₁ reaches the threshold voltage V_(TH) of the flip-flop FF at time t₁, the flip-flop FF is set to 1, and the high level output signal V_(OUT) is obtained as shown in FIG. 9(f). The delay time at the starting edge is T_(dLH) =T₁ -t₀.

On the other hand, when the digital input signal V_(IN) changes to low level at time t₂, the potential at the point (e) which is the output of the inverter INV₂ changes also to low level, where the difference t₂ -t₀ is equal to the pulse width of the digital input pulse. The potential at the point (e) is applied to the gate G₁₂ of the FET M₁₂ of the second delay circuit D₂, then, the potential at the point (f) at one end of the capacitor C₂ provides the ramp voltage which begins to increase at time t₂ as shown in FIG. 9(e). The ramp voltage reaches the threshold voltage V_(TH) of the flip-flop FF at time t₃, and then, that flip-flop changes to reset state. Thus, the output of the inverter INV₃ changes to low level as shown in FIG. 9(f). The duration between t₃ and t₂ is the delay time of the rear edge of the digital input pulse.

The first delay time T_(dLH) and the second delay time T_(dHL) are adjusted by the resistance of the resistors R₁₀ and R₂₀, and the capacitance of the capacitors C₁ and C₂. When T_(dLH) is equal to T_(dHL), the pulse width of the delayed output pulse V_(OUT) is the same as the pulse width of the input pulse V_(IN). When T_(dLH) differs from T_(dHL), then, the pulse width of the output pulse V_(OUT) may be designed arbitrarily.

It should be appreciated that the embodiment of FIGS. 8 and 9 can provide a delay time which is free from temperature variation, power supply voltage variation, and/or process variation. And, further, the pulse width of the delayed output pulse may be designed arbitrarily.

It should be appreciated of course that a current mirror circuit mentioned in FIG. 6 may be combined to the embodiment of FIGS. 8 and 9. The bias circuit 1 in FIG. 6 may be common to the first delay circuit D₁ and the second delay circuit D₂.

FIG. 10 shows a circuit diagram of still another embodiment of the delay circuit according to the present invention, and FIG. 11 shows the operational waveforms of FIG. 10. Similar to the embodiment of FIG. 8, the digital input signal V_(IN) in FIG. 10 is separated to two paths by using an inverter INV₁. The first delay circuit R₁ functions to delay the beginning edge of an input pulse, and the second delay circuit R₂ functions to delay the rear edge of an input pulse. The logic circuit Q₁ combines the outputs of the first delay circuit R₁ and the second delay circuit R₂, so that the pulse width of the delay output pulse V_(OUT) may be the same as that of the input pulse V_(IN), or may be designed arbitrarily. The structure of the first delay circuit R₁ and the second delay circuit R₂ is essentially the same as that of FIG. 4. The flip-flop FF in the logic circuit Q₁ is composed of NAND gates.

The first delay circuit R₁ has an operational amplifier A₁₀, the resistor R₁₀, the first MOSFET M₁₁, the second MOSFET M₂₁, and the capacitor C₁. The gate G₁₁ of the first FET M₁₁ receives the digital input signal V_(IN). The second delay circuit C₂ has an operational amplifier A₂₀, a resistor R₂₀, a first MOSFET M₁₂, a second MOSFET M₂₂, and a capacitor C₂. The gate G₁₂ of the first FET M₁₂ receives the digital input signal V_(IN) in the reversed polarity inverted by the inverter INV₁.

The logic circuit Q₁ has a flip-flop FF which is a RS (set-reset) flip-flop having a pair of NAND gates NAND₁ and NAND₂, and is set to one state by low level output signal of the first delay circuit R₁, and is reset to zero state by the low level output signal of the second delay circuit R₂. The output of the NAND₂ is coupled with the output terminal V_(OUT) through the inverter INV₃.

The negative inputs (-) of the operational amplifiers A₁₀ and A₂₀ are connected to the source S₂₁ and the source S₂₂ of the second FET M₂₁ and M₂₂, respectively, and are grounded through the resistors R₁₀, and F₂₀, respectively. The outputs of those amplifiers are connected to the gates G₂₁ and G₂₂ of the second FET M₂₁ and M₂₂, respectively.

The positivie inputs (+) of the operational amplifiers A₁₀ and A₂₀ are commonly connected to the output of the bias means 1.

When a digital input signal V_(IN) becomes high level at time t₀ as shown in FIG. 11(a), the potential at the point (d) in the first delay circuit R₁ begins to decrease as shown in FIG. 11(b) as mentioned in accordance with the embodiment of FIG. 4, since said input signal V_(IN) is applied to the gate G₁₁ of the first FET M₁₁ of the first delay circuit D₁. When the ramp voltage at the point (d) reaches the threshold voltage of the flip-flop FF at time t₁, the flip-flop FF is set to one state at time t₁, and the high level output signal V_(OUT) is obtained at the output terminal through the inverter INV₃. The delay time is T_(dLH) between t₀ and t₁.

On the other hand, when the digital input signal V_(IN) returns to low level at time t₂ which is after the pulse width of the input digital signal from time t₀, the potential at the point (e) at the output of the inverter INV₁ becomes high level as shown in FIG. 11(c). The signal at the point (e) is applied to the gate G₁₂ of the first FET M₁₂ in the second delay circuit R₂, and therefore, the potential at the point (f) begins to decrease as shown in FIG. 11(d). When that potential reaches the threshold voltage of the flip-flop FF at time t₃, the flip-flop FF is set to one state at time t₃, and the low level output signal V_(OUT) is obtained through the inverter INV₃ as shown in FIG. 11(e). The delay time T_(dHL) is the time between t₃ and t₂.

If the delay time T_(dLH) is equal to the delay time T_(dHL) by appropriate selection of the resistance of the resistors R₁₀ and R₂₀, and the capacitance of the capacitors C₁ and C₂, the pulse width of the input signal V_(IN) is equal to the pulse width of the output pulse V_(OUT). Of course, the pulse width of an output pulse may be designed arbitrarily by designing the delay times T_(dLH) and T_(dHL) independently.

It should be appreciated of course that the combination of the circuit of FIG. 10 and a current mirror circuit as mentioned in accordance with FIG. 7 is possible. At that case, the bias circuit having an operational amplifier A₀, a resistor R_(c), and a pair of operational amplifiers M₂ and M₃ in FIG. 7 may be common to both the first delay circuit R₁ and the second delay circuit R₂.

A delay line having a plurality of taps may be constituted by a plurality of delay circuits of FIG. 8 or FIG. 10. That delay line is used in a transversal filter. In that case, the inverter INV₁ is omitted by taking a first input to the gate G₁₁ at the input of the inverter INV₃, and a second input to the gate G₁₂ at the output of the inverter INV₃. The omission of an input inverter INV₁ is advantageous to reduce the load of the output inverter INV₃ which would provide an additional delay time in case of heavy load.

From the foregoing it will now be apparent that a new and improved delay circuit has been found. It should be understood of course that the embodiments disclosed are merely illustrative and are not intended to limit the scope of the invention. Reference should be made to the appended claims, therefore, rather than the specification as indicating the scope of the invention. 

What is claimed is:
 1. A delay circuit comprising at least one ramp generator for providing a ramp voltage initiated by at a digital input signal, a logic circuit accepting said ramp voltage and providing a digital output signal which is delayed by a predetermined duration from said digital input signal when said ramp voltage reaches a predetermined threshold voltage, and a bias means for providing bias voltage to said ramp generator,said ramp generator comprising;a switching means comprising a first MOSFET which is switched ON and OFF by said digital input signal, a charge/discharge means comprising a second MOSFET, a resistor which is connected in series to a drain-source circuit of said second MOSFET, and an operational amplifier with an output coupled with a gate of said second MOSFET, a negative input coupled with the junction of said resistor and said second MOSFET, and a positive input which accepts a bias voltage, a capacitor which is charged and/or discharged through said charge/discharge means, and provides said ramp voltage across the capacitor, and a current mirror circuit coupled with said charge/discharge means; said capacitor being charged and/or discharged through said current mirror circuit which provides the same current as that in the charge/discharge means; said bias means comprising at least one of means for providing voltage proportional to temperature variation and means for providing voltage proportional to said threshold voltage of said logic circuit.
 2. A delay circuit according to claim 1, wherein two ramp generators are provided so that a digital input signal is applied to each of the ramp generators in opposite polarities to each other, and wherein said logic circuit has an flip-flop which is set and reset by outputs of the respective ramp generators.
 3. A delay circuit according to claim 1, wherein said bias means comprises;a first compensation voltage generator for providing voltage which changes linearly according to temperature change, a second compensation voltage generator for providing voltage which is free from temperature change, a third compensation voltage generator for providing voltage which is proportional to said threshold voltage of said logic circuit, a combiner for combining outputs of the above three compensation means, and means for suppressing variation of power supply voltage from the output of said combiner.
 4. A delay circuit according to claim 3, wherein said current mirror circuit has a third MOSFET and a fourth MOSFET with respective gates connected together, respective sources connected together, a gate of the third MOSFET being connected to a drain of the third MOSFET, and the third MOSFET being coupled with said charge/discharge means, and the fourth MOSFET being coupled with said capacitor.
 5. A delay circuit according to claim 1, wherein said logic circuit is an inverter.
 6. A delay circuit according to claim 1, wherein one end of said capacitor is grounded, and the other end of said capacitor is coupled with power supply voltage through said charge/discharge means.
 7. A delay circuit according to claim 1, wherein one end of said capacitor is grounded, and the other end of said capacitor is coupled with power supply voltage through said switching means.
 8. A delay circuit according to claim 1, wherein said means for providing voltage proportional to temperature change has a pair of bipolar transistors in diode connection and an operational amplifier receiving respective outputs of said bipolar transistors.
 9. A delay circuit comprising at least one ramp generator for providing a ramp voltage initiated by a digital input signal, a logic circuit accepting said ramp voltage and providing a digital output signal which is delayed by a predetermined duration from said digital input signal when said ramp voltage reaches a predetermined threshold voltage, and a bias means for providing bias voltage to said ramp generator,said ramp generator comprising;a switching means comprising a first MOSFET which is switched ON and OFF by said digital input signal, a charge/discharge means comprising a second MOSFET, a resistor which is connected in series to a drain-source circuit of said second MOSFET, and an operational amplifier with an output coupled with a gate of said second MOSFET, a negative input coupled with the junction of said resistor and said second MOSFET, and a positive input which accepts a bias voltage, and a capacitor which is charged and/or discharged through said charge/discharge means, and provides said ramp voltage across the capacitor, said bias means comprising at least one of means for providing voltage proportional to temperature variation and means for providing voltage proportional to said threshold voltage of said logic circuit, said means for providing voltage proportional to temperature change including a pair of bipolar transistors in diode connection and an operational amplifier receiving respective outputs of said bipolar transistors.
 10. A delay circuit according to claim 9, wherein a current mirror circuit is coupled with said charge/discharge means, and said capacitor is charged and/or discharged through said current mirror circuit which provides the same current as that in the charge/discharge means.
 11. A delay circuit according to claim 9, wherein two ramp generators are provided so that a digital input signal is applied to each of the ramp generators in opposite polarities to each other, and wherein said logic circuit has a flip-flop which is set and reset by outputs of the respective ramp generators.
 12. A delay circuit according to claim 9, wherein said bias means comprises;a first compensation voltage generator for providing voltage which changes linearly according to temperature change, a second compensation voltage generator for providing voltage which is free from temperature change, a third compensation voltage generator for providing voltage which is proportional to said threshold voltage of said logic circuit, a combiner for combining outputs of the above three compensation means, and means for suppressing variation of power supply voltage from the output of said combiner.
 13. A delay circuit according to claim 9, wherein said logic circuit is an inverter.
 14. A delay circuit according to claim 9, wherein one end of said capacitor is grounded, and the other end of said capacitor is coupled with power supply voltage through said charge/discharge means.
 15. A delay circuit according to claim 9, wherein one end of said capacitor is grounded, and the other end of said capacitor is coupled with power supply voltage through said switching means.
 16. A delay circuit according to claim 12, wherein said current mirror circuit has a third MOSFET and a fourth MOSFET with respective gates connected together, respective sources connected together, a gate of the third MOSFET being connected to a drain of the third MOSFET, and the third MOSFET being coupled with said charge/discharge means, and the fourth MOSFET being coupled with said capacitor. 